Architecture of Low Dropout Linear Voltage Regulators

Linear voltage regulators have been valuable system components since the early days. One reason is the relatively low noise characteristic vis-à-vis the switching type of regulator. Others are a low parts count and overall simplicity compared to discrete solutions. But, because of their power losses, these linear regulators have also been known for being relatively inefficient.

More recently however, linear IC regulators have been developed with more liberal (i.e., lower) limits on minimum input-output voltage. This voltage, known more commonly as dropout voltage, has led to what is termed the Low DropOut regulator, or more popularly, the LDO. Dropout voltage (VMIN) is defined simply as that minimum input-output differential where the regulator undergoes a 2% reduction in output voltage. For example, if a nominal 5.0V LDO output drops to 4.9V (-2%) under conditions of an input-output differential of 0.5V, by this definition the LDO’s VMIN is 0.5V.

The lower the voltage allowable across a regulator while still maintaining a regulated output, the less power the regulator dissipates as a result. A low regulator dropout voltage is the key to this, as it takes this lower dropout to maintain regulation as the input voltage lowers. In performance terms, the bottom line for LDOs is simply that more useful power is delivered to the load and less heat is generated in the regulator. LDOs are key elements of power systems that must provide stable voltages from batteries, such as portable computers, cellular phones, etc. This is simply because they maintain their regulated output down to lower points on the battery’s discharge curve. Or, within classic mainspowered raw DC supplies, LDOs allow lower transformer secondary voltages, reducing system susceptibility to shutdown under brownout conditions as well as allowing cooler operation.

If we call the total power PD, this then becomes:

PD = VIN - VOUT IL + VIN,Iground.

Obviously, the magnitude of the load current and the regulator dropout voltage both greatly influence the power dissipated. However, it is also easy to see that for a given IL, as the dropout voltage is lowered, the first term of PD is reduced. With an intermediate dropout voltage rating of 1V, a 1A load current will produce 1W of heat in this regulator, which may require a heat sink for continuous operation. It is this first term of the regulator power which usually predominates, at least for loaded regulator conditions.

The second term, being proportional to Iground (typically only 1-2 mA, sometimes even less) usually only becomes significant when the regulator is unloaded, and the regulator’s quiescent or standby power then produces a constant drain on the source VIN.

However, it should be noted that in some types of regulators (notably those which have very low pass devices such as lateral PNP transistors) the I ground current under load can actually run quite high. This effect is worst at the onset of regulation, or when the pass device is in saturation, and can be noted by a sudden I ground current “spike”, where the current jumps upward abruptly from a lower low level. All LDO regulators using bipolar transistor pass devices which can be saturated (such as PNPs) can show this effect. It is much less severe in PNP regulators using vertical PNPs (since these have a higher intrinsic ) and doesn’t exist to any major extent in PMOS LDOs (since PMOS transistors are controlled by voltage level, not current).

In the example shown, the regulator delivers 5V × 1A, or 5W to the load. With a dropout voltage of 1V, the input power is 6V times the same 1A, or 6W. In terms of power efficiency, this can be calculated as:

where POUT and PIN are the total output and input powers, respectively.

In these sample calculations, the relatively small portion of power related to Iground will be ignored for simplicity, since this power is relatively small. In an actual design, this simplifying step may not be justified.

In the case shown, the efficiency would be 100 × 5/6, or about 83%. But by contrast, if an LDO were to be used with a dropout voltage of 0.1V instead of 1V, the input voltage can then be allowed to go as low as 5.1V. The new efficiency for this condition then becomes 100 × 5/5.1, or 98%. It is obvious that an LDO can potentially greatly enhance the power efficiency of linear voltage regulator systems.

A traditional LDO architecture is shown in below Figure, and is generally representative of actual parts employing either a PNP pass device as shown, or alternately, a PMOS device.

In DC terms, perhaps the major issue is the type of pass device used, which influences dropout voltage and ground current. If a lateral PNP device is used for Q1, the will be low, sometimes only on the order or 10 or so. Since Q1 is driven from the collector of Q2, the relatively high base current demanded by a lateral PNP results in relatively high emitter current in Q2, or a high Iground. For a typical lateral PNP based regulator operating with a 5V/150mA output, Iground will be typically ~18mA, and can be as high as 40mA. To compound the problem of high Iground in PNP LDOs, there is also the “spike” in Iground, as the regulator is operating within its dropout region. Under such conditions, the output voltage is out of tolerance, and the regulation loop forces higher drive to the pass device, in an attempt to maintain loop regulation. This results in a substantial spike upward in Iground, which is typically internally limited by the regulator’s saturation control circuits.

PMOS pass devices do not demonstrate a similar current spike in Iground, since they are voltage controlled. But, while devoid of the Iground spike, PMOS pass devices do have some problems of their own. Problem number one is that high quality, low RON, low threshold PMOS devices generally aren’t compatible with many IC processes. This makes the best technical choice for a PMOS pass device an external part, driven from the collector of Q2 in the figure. This introduces the term “LDO controller”, where the LDO architecture is completed by an external pass device. While in theory NMOS pass devices would offer lower RON choice options, they also demand a boosted voltage supply to turn on, making them impractical for a simple LDO. PMOS pass devices are widely available in low both RON and low threshold forms, with current levels up to several amperes. They offer the potential of the lowest dropout of any device, since dropout can always be lowered by picking a lower RON part.

The dropout voltage of lateral PNP pass devices is reasonably good, typically around 300mV at 150mA, with a maximum of 600mV. These levels are however considerably bettered in regulators using vertical PNPs, which have a typical of 150 at currents of 200mA. This leads directly to an Iground of 1.5mA at the 200mA output current. The dropout voltage of vertical PNPs is also an improvement vis-àvis that of the lateral PNP regulator, and is typically 180mV at 200mA, with a maximum of 400mV.

There are also major AC performance issues to be dealt with in the LDO architecture shown above.

This topology has an inherently high output impedance, due to the operation of the PNP pass device in a common-emitter (or common-source with a PMOS device) mode. In either case, this factor causes the regulator to appear as a high source impedance to the load.

The internal compensation capacitor of the regulator, CCOMP, forms a fixed frequency pole, in conjunction with the gm of the error amplifier. In addition, load capacitance CL forms an output pole, in conjunction with RL. This particular pole, because it is a second (and sometimes variable) pole of a two-pole system, is the source of a major LDO application problem. The CL pole can strongly influence the overall frequency response of the regulator, in ways that are both useful as well as detrimental. Depending upon the relative positioning of the two poles in the frequency domain, along with the relative value of the ESR of capacitor CL, it is quite possible that the stability of the system can be compromised for certain combinations of CL and ESR. Note that CL is shown here as a real capacitor, which is actually composed of a pure capacitance plus the series parasitic resistance ESR. Without a heavy duty exercise into closed-loop stability analysis, it can safely be said that LDOs, like other feedback systems, need to satisfy certain basic stability criteria. One of these is the gain-versus-frequency rate-of-change characteristic in the region approaching the system’s unity loop gain crossover point. For the system to be closed loop stable, the phase shift must be less than 180at the point of unity gain. In practice, a good feedback design needs to have some phase margin, generally 45or more to allow for various parasitic effects. While a single pole system is intrinsically stable, two pole systems are not necessarily so—they may in fact be stable, or they may also be unstable. Whether or not they are stable for a given instance is highly dependent upon the specifics of their gain-phase characteristics. If the two poles of such a system are widely separated in terms of frequency, stability may not be a serious problem.

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